In the field of VLSI microelectronic circuits, many digital systems require a certain clock duty cycle (i.e. 50/50%, 40/60%) for proper operation. However, such clock duty cycles are not always readily available. A clock with an inappropriate duty cycle may cause the digital system to fail or force the system to run at a lower clock speed. Although many digital systems desire a 50/50% duty cycle, not all digital systems necessarily desire the same clock duty cycle. Depending on the source of the clock, the duty cycle may not always be known or predictable. Hence, duty cycle correction is needed.
One such approach to duty cycle correction is to use a phase-locked loop to synthesize a clock at double the input frequency, and then to divide down by two to obtain a 50/50% duty cycle. This approach requires the building of a phase-locked loop, which is complex in design, large in area, and high in power. This approach also only limits the output duty cycle to 50/50%.
In U.S. Pat. No. 5,317,202, Waizman discloses a 50% duty-cycle clock generator, which is limited to generating only a 50% duty cycle and its implementation complicated.
In U.S. Pat. No. 5,572,158, Lee et al describe an amplifier circuit with active duty cycle correction to produce a predetermined duty cycle. However, such a circuit uses three operational amplifiers, thus being relatively high in power consumption and large in area.
In U.S. Pat. No. 5,757,218, Blum describes a circuit and a method for signal duty cycle correction, which involves the use of a ring oscillator counter to produce adjustable delays. In order for this approach to have sufficient duty cycle resolution, the ring oscillator must operate at a frequency much higher than the input clock, meaning a large use of power. Lower operating speeds would mean degradation in the duty cycle resolution.
In U.S. Pat. No. 5,550,499, Eitrheim describes an adjustable duty cycle clock generator using multiplexers to adjust the delay in a delay line. The problem with this approach is that the amount of delay needed is not known by the circuit and must be determined elsewhere either through measurement or other dynamic means. This circuit cannot self-correct for the appropriate duty cycle.
In U.S. Pat. No. 5,617,563, Banerjee et al describe a duty-cycle independent tunable clock that uses an adjustable delay line in conjunction with a flip-flop. However, the described circuit is limited by using a fixed delay, once adjusted (by blowing out fuses through a laser), thereby providing a duty cycle for a given adjustment which directly depends on the clock input. Furthermore, the use of blowing out fuses for changing the duty cycle is relatively expensive and demands a larger overall circuit. Once the fuses are set to provide a desired duty cycle for a particular clock frequency, they cannot be changed again to operate with a different frequency or to obtain a different duty cycle.
In U.S. Pat. No. 5,477,180, Chen describes a circuit and a method for generating a clock signal wherein the duty cycle is adjusted independent of the input clock frequency by adjusting a bias voltage at the driver circuit of the output clock, which is driven by the input clock. This bias voltage is generated by a differential amplifier driven by two voltage-adjusted inputs using two adjustable tapped resistors. In Chen's approach, however, at least one operational amplifier and four resistors are required resulting in a relatively large circuit area and high power. Furthermore, the resulting output clock signal is shaped by an RC time constant giving relatively long rise/fall times, especially when duty cycles far beyond 50/50% are desired. Chen teaches that for duty cycles far beyond 50/50%, a few of the described circuits can be cascaded for better rise/fall times. This would require more operational amplifiers and more resistors, hence larger circuit size and greater power consumption. Moreover, there is no provision in Chen's approach for adjusting the duty cycles `on the fly`, i.e. whenever desired by the user.
In view of the limitations of the prior art reviewed above, it would be desirable to provide all economical circuit and method for regulating a steady state clock duty cycle over a relatively wide range of selectable duty cycles, without being dependent on an actual input clock frequency value.